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HSP43881
Data Sheet May 1999 File Number
2758.4
Digital Filter
The HSP43881 is a video speed Digital Filter (DF) designed to efficiently implement vector operations such as FIR digital filters. It is comprised of eight filter cells cascaded internally and a shift and add output stage, all in a single integrated circuit. Each filter cell contains a 8 x 8-bit multiplier, three decimation registers and a 26-bit accumulator. The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8 bits. The HSP43881 has a maximum sample rate of 30MHz. The effective multiply accumulate (mac) rate is 240MHz. The HSP43881 DF can be configured to process expanded coefficient and word sizes. Multiple DFs can be cascaded for larger filter lengths without degrading the sample rate or a single DF can process larger filter lengths at less than 30MHz with multiple passes. The architecture permits processing filter lengths of over 1000 taps with the guarantee of no overflows. In practice, most filter coefficients are less than 1.0, making even larger filter lengths possible. The DF provides for 8-bit unsigned or two's complement arithmetic, independently selectable for coefficients and signal data. Each DF filter cell contains three resampling or decimation registers which permit output sample rate reduction at rates of 1/2, 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as matrix multiplication and N x N spatial correlations/convolutions for image processing applications.
Features
* Eight Filter Cells * 0MHz to 30MHz Sample Rate * 8-Bit Coefficients and Signal Data * 26-Bit Accumulator Per Stage * Filter Lengths Over 1000 Taps * Expandable Coefficient Size, Data Size and Filter Length * Decimation by 2, 3 or 4
Applications
* 1-D and 2-D FIR Filters * Radar/Sonar * Adaptive Filters * Echo Cancellation * Complex Multiply-Add * Sample Rate Converters
Ordering Information
PART NUMBER HSP43881JC-20 HSP43881JC-25 HSP43881JC-30 HSP43881GC-20 HSP43881GC-25 HSP43881GC-30 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 84 Ld PLCC 84 Ld PLCC 84 Ld PLCC 85 Ld PGA 85 Ld PGA 85 Ld PGA PKG. NO. N84.1.15 N84.1.15 N84.1.15 G85.A G85.A G85.A
Block Diagram
VCC DIENB CIENB DCMO - 1 ERASE TCCI CIN0 - 7 RESET CLK ADR0 - 2 RESET CLK SHADD SENBL SENBH 8 5 VSS DIN0 - DIN7 TCS 8 5 8 DF FILTER CELL 0 5 3 MUX ADR0, ADR1, ADR2 2 26 OUTPUT STAGE 2 SUM0 - 25 26 26 8 8 DF FILTER CELL 1 26 8 8 DF FILTER CELL 2 26 8 8 DF FILTER CELL 3 26 8 8 DF FILTER CELL 4 26 8 8 DF FILTER CELL 5 26 8 8 DF FILTER CELL 6 26 8 8 DF FILTER CELL 7 26 TCCO 8 COUT0 - 7 COENB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HSP43881 Pinouts
85 PIN GRID ARRAY (PGA) TOP VIEW, PINS DOWN
1 A VSS VCC 2 3 4 5 6 DIN6 7 DIN3 8 DIN0 9 TCCI 10 VCC CIN6 11 VSS CIN4
COENB VCC
RESET DIN7
B
COUT7 TCCO ERASE TCS ALIGN PIN
DIN1
DIN2 CIENB CIN7
C COUT5 COUT6
DIENB DIN5
DIN4
CIN5
CIN3 VCC
D COUT3 COUT4
CIN2
E COUT1
VSS
COUT2
CIN1
CIN0 SENBL VCC VSS
F G
VSS
COUT0 SHADD CLK
SUM0
ADR2 DCM0
SUM1 SUM3 SUM2
H J
ADR1 VCC
ADR0 SUM25 SUM20 SUM17 SUM16
SUM5 SUM4 SUM7 VSS
K SENBH SUM24
VSS
VCC
SUM19
VSS
SUM15 SUM12 SUM10 SUM8 SUM6
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
VCC
SUM13
VSS
SUM11 SUM9
HSP43881 TOP VIEW, PINS UP
1 2 3 4 5 6 7 8 9 10 11
L DCM1 K SENBH J VCC H ADR1 G ADR2 F VSS E COUT1 D COUT3 C COUT5 COUT6 B VCC A VSS COENB VCC RESET DIN7 DIN6 DIN3 DIN0 CIN8 VCC VSS COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4 ALIGN PIN DIENB DIN5 DIN4 CIN5 CIN3 COUT4 CIN2 VCC VSS COUT2 CIN1 CIN0 SENBL COUT0 SHADD SUM0 VCC VSS DCM0 CLK SUM1 SUM3 SUM2 ADR0 SUM5 SUM4 SUM25 SUM20 SUM17 SUM16 SUM7 VSS SUM24 VSS VCC SUM19 VSS SUM15 SUM12 SUM10 SUM8 SUM6 SUM23 SUM22 SUM21 SUM18 SUM14 VCC SUM13 VSS SUM11 SUM9
2
HSP43881 Pinouts
(Continued) 84 LEAD PLCC PACKAGE BOTTOM VIEW
SHADD SENBH ADDR0 ADDR1 ADDR2 COUT0 COUT1 COUT2 COUT3 COUT4 COUT5 SUM24 SUM25 DCM1 DCM0
VCC
CLK
11 10 SUM23 SUM22 VCC SUM21 SUM20 SUM19 SUM18 VSS SUM17 SUM16 VCC SUM15 SUM14 SUM13 SUM12 VSS SUM11 SUM10 SUM9 SUM8 SUM7 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 COUT6 COUT7 VSS TCCO COENB VCC ERASE RESET DIENB TCS DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB TCCI VCC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
SUM6
SUM5
SUM4
SUM3
SUM2
SUM1
SUM0
NOTE: An overbar on a signal name represents an active LOW signal.
3
SENBL
CIN7
VSS
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VSS
HSP43881 Pin Description
SYMBOL VCC PIN NUMBER A3, A10, B1, D11, F10, J1, K4, L7 A1, A11, E2, F1, E11, H11, K3, K6, L9 G3 A58, B67, C67 I I TYPE +5V Power Supply Input. DESCRIPTION
VSS
Power Supply Ground Input.
CLK DIN0-7
The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz. These eight inputs are the data sample input bus. Eight bit data samples are synchronously loaded through these pins to the X register of each filter cell simultaneously. The DIENB signal enables loading, which is synchronous on the rising edge of the clock signal. The TCS input determines the number system interpretation of the data input samples on pins DIN0-7 as follows: TCS = Low Unsigned Arithmetic. TCS = High Two's Complement Arithmetic. The TCS signal is synchronously loaded into the X register in the same way as the DIN0-7 inputs. A low on this enables the data sample input bus (DIN0-7) to all the filter cells. A rising edge of the CLK signal occurring while DIENB is low will load the X register of every filter cell with the 8-bit value present on DIN0-7. A high on this input forces all the bits of the data sample input bus to zero; a rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This signal is latched inside the DF, delaying its effect by one clock internal to the DF. Therefore, it must be low during the clock cycle immediately preceding presentation of the desired data on the DIN0-7 inputs. Detailed operation is shown in later timing diagrams. These eight inputs are used to input the 8-bit coefficients. The coefficients are synchronously loaded into the C register of filter CELL 0 if a rising edge of CLK occurs while CIENB is low. The CIENB signal is delayed by one clock as discussed below. The TCCI input determines the number system interpretation of the coefficient inputs on pins CIN07 as follows: TCCI = LOW E Unsigned Arithmetic. TCCI = HIGH E Two's Complement Arithmetic. The TCCI signal is synchronously loaded into the C register in the same way as the CIN0-7 inputs. A low on this input enable the C register of every filter cell and the D registers (decimation) of every filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while CIENB is low will load the C register and appropriate D registers with the coefficient data present at their inputs. This provides the mechanism for shifting the coefficients from cell to cell through the device. A high on this input freezes the contents of the C register and the D registers ignoring the CLK signal. This signal is latched and delayed by one clock internal to the DF. Therefore, it must be low during the clock cycle immediately preceding presentation of the desired coefficient of the CIN07 inputs. Detailed operation is shown in the Timing Diagrams Section. These eight three-state outputs are used to output the 8-bit coefficients from filter cell 7. These outputs are enabled by the COENB signal low. These outputs may be tied to the CIN0-7 inputs of the same DF to recirculate the coefficients, or they may be tied to the CIN0-7 inputs of another DF to cascade DFs for longer filter lengths. The TCCO three-state output determines the number system representation of the coefficients output on COUTO-7. It tracks the TCCI signal to this same DF. It should be tied to the TCCI input of the next DF in a cascade of DFs for increased filter lengths. This signal is enabled by COENB low. A low on the COENB input enables the COUT0-7 and the TCCO output. A high on this input places all these outputs in their high impedance state.
TCS
B5
I
DIENB
C5
I
CIN0-7
B9-11, C10-11, D10, E9-10 A9
I
TCCI
I
CIENB
B8
I
COUT0-7
B2, C1-2, D1-2, E1, E3, F2 B3
O
TCCO
O
COENB
A2
I
4
HSP43881 Pin Description
SYMBOL DCM0-1 (Continued) TYPE DESCRIPTION These two inputs determine the use of the internal decimation registers as follows: DCM1 DCM0 Decimation Function 0 0 Decimation Registers not used. 0 1 One Decimation Register is used. 1 0 Two Decimation Registers are used. 1 1 Three Decimation Registers are used. The coefficients pass from cell to cell at a rate determined by the number of decimation registers used. When no decimation registers are used, coefficients move from cell to cell on each clock. When one decimation register is used, coefficients move from cell to cell on every other clock, etc. These signals are latched and delayed by one clock internal to the DF. O These 26 three-state outputs are used to output the results of the internal filter cell computations. Individual filter cell results or the result of the shift and add output stage can be output. If an individual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines whether the selected filter cell result or the output stage adder result is output. The signals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result, respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However, individual enables are provided to facilitate use with a 16-bit bus. A low on this input enables result bits SUM16-25. A high on this input places these bits in their high impedance state. A low on this input enables result bits SUM0-15. A high on this input places these bits in their high impedance state. These inputs select the one cell whose accumulator will be read through the output bus (SUM0-25) or added to the output stage accumulator. They also determine which accumulator will be cleared when ERASE is low. For selection of which accumulator to read through the output bus (SUM0-25) or which to add to the output stage accumulator, these inputs are latched in the DF and delayed by one clock internal to the device. If the ADR0-2 lines remain at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock, when ADR0-1 selects the cell, will be output. This does not hinder normal operation since the ADR0-1 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock. The SHADD input controls the activation of the shift-and-add operation in the output stage. This signal is latched in the DF and delayed by one clock internal to the device. A detailed explanation is given in the DF Output Stage Section. A low on this input synchronously clears all the internal registers, except the cell accumulators. It can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF and delayed by one clock internal to the DF. A low on this input synchronously clears the cell accumulator selected by the ADR0-1 signals. If RESET is also low simultaneously, all cell accumulators are cleared. Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit.
PIN NUMBER G2, L1
SUM0-25
J2, J5-8, J10, K2, K5-11, L-26, L8, L10-11
SENBH SENBL ADR0-2
K1 E11 G1, H1-2
I I I
SHADD
F3
I
RESET
A4
I
ERASE ALIGN PIN
B4 C3
I
Functional Description
The Digital Filter Processor (DF) is composed of eight filter cells cascaded together and an output stage for combining or selecting filte5r cell outputs (See Block Diagram). Each filter cell contains a multiplier accumulator and several registers (Figure 1). Each 8-bit coefficient is multiplied by an 8-bit data sample, with the result added to the 26-bit accumulator contents. The coefficient output of each cell is cascaded to the coefficient input of the next cell to its right.
COUT0-7. With no decimation, the coefficient moves directly from the C register to the output, and is valid on the clock following its entrance. When decimation is selected the coefficient exit is delayed by 1, 2 or 3 clocks by passing through one or more decimation registers (D1, D2 or D3). The combination of D registers through which the coefficient passes is determined by the state of DCM0 and DCM1. The output signals (COUT0-7) are connected to the CIN0-7 inputs of the next cell to its right. The COENB input signal enables the COUT0-7 outputs of the right most cell to the COUT-07 pins of the device. The C and D registers are enabled for loading by CIENB. Loading is synchronous with CLK when CIENB is low. Note that
DF Filter Cell
An 8-bit coefficient (CIN0-7) enters each cell through the C register on the left and exits the cell on the right as signals
5
HSP43881
CIENB is latched internally. It enables the register for loading after the next CLK following the onset of CIENB low. Actual loading occurs on the second CLK following the onset of CIENB low. Therefore, CIENB must be low during the clock cycle immediately preceding presentation of the coefficient on the CIN0-7 inputs. In most basic FIR operations, CIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When CIENB is high, the coefficients are frozen. These registers are cleared synchronously under control of RESET, which is latched and delayed exactly like CIENB. The output of the C register (C0-8) is one input to 8 x 8 multiplier. The other input to the 8 x 8 multiplier comes from the output of the X register. This register is loaded with a data sample from the device input signals DIN0-7 discussed above. The X register is enabled for loading by DIENB. Loading is synchronous with CLK when DIENB is low. Note that DIENB is latched internally. It enables the register for loading after the next CLK following the onset of DIENB low. Actual loading occurs on the second CLK following the onset of DIENB low; therefore, DIENB must be low during the clock cycle immediately preceding presentation of the data sample on the DIN0-7 inputs. In most basic FIR operations, DIENB will be low throughout the process, so this latching and delay sequence is only important during the initialization phase. When DIENB is high, the X register is loaded with all zeros. The multiplier is pipelined and is modeled as a multiplier core followed by two pipeline registers, MREG0 and MREG1 (Figure 1). The multiplier output is sign extended and input as one operand of the 26-bit adder. The other adder operand is the output of the 26-bit accumulator. The adder output is loaded synchronously into both the accumulator and the TREG. The TREG loading is disabled by the cell select signal, CELLn, where n is the cell number. The cell select is decoded from the ADR0-2 signals to generate the TREG load enable. The cell select is inverted and applied as the load enable to the TREG. Operation is such that the TREG is loaded whenever the cell is not selected. Therefore, TREG is loaded every clock except the clock following cell selection. The purpose of the TREG is to hold the result of a sum of products calculation during the clock when the accumulator is cleared to prepare for the next sum of products calculation. This allows continuous accumulation without wasting clocks. The accumulator is loaded with the adder output every clock unless it is cleared. It is cleared synchronously in two ways. When RESET and ERASE are both low, the accumulator is cleared along with all other registers on the device. Since ERASE and RESET are latched and delayed one clock internally, clearing occurs on the second CLK following the onset of both ERASE and RESET low. The second accumulator clearing mechanism clears a single accumulator in a selected cell. The cell select signal, CELLn, decoded from ADR0-2 and the ERASE signal enable clearing of the accumulator on the next CLK. The ERASE and RESET signals clear the DF internal registers and states as follows:
ERASE 1 1 RESET 1 0 CLEARING EFFECT No clearing occurs, internal state remains same. RESET only active, all registers except accumulators are cleared, including the internal pipeline registers. ERASE only active, the accumulator whose address is given by the ADR0-2 inputs is cleared. Both RESET and ERASE active, all accumulators, as well as all other registers are cleared.
0
1
0
0
The DF Output Stage
The output stage consists of a 26-bit adder, 26-bit register, feedback multiplexer from the register to the adder, an output multiplexer and a 26-bit three-state driver stage (Figure 2). The 26-bit output adder can add any filter cell accumulator result to the 18 most significant bits of the output buffer. This result is stored back in the output buffer. This operation takes place in one clock period. The eight LSBs of the output buffer are lost. The filter cell accumulator is selected by the ADR0-2 inputs. The 18 MSBs of the output buffer actually pass through the zero mux on their way to the output adder input. The zero mux is controlled by the SHADD input signal and selects either the output buffer 18 MSBs or all zeros for the adder input. A low on the SHADD input selects zero. A high on the SHADD input selects the output buffer MSBs, thus, activating the shift and add operation. The SHADD signal is latched and delayed by one clock internally.
6
HSP43881
DCM1.D DCM0.D RESET.D CIENB.D TCCI 7 CIN0-7 LD CLR C REG 0-7 C0-7 C.TCCI LD CLR D1 REG 1 MUX CLK CLK 0 B RESET.D DIENB.D TCS 7 DIN0-7 CLK MREG0 DCM1.D DCM0.D RESET.D DIENB.D CIENB.D ADR0.D ADR1.D ADR2.D ERASE.D ADDER ACC0-25 ERASE.D ACC CLR CELLn CLK ACC.D0-25 0-17 SIGN EXTENSION 18-25 MREG1 CLR RESET.D CLR CLK LD CLR X REG X0-8 C MULTIPLIER X CORE P0-17 C0-8 D.TCCI D0-7 CLK 0 LD CLR D2 REG LD CLR D3 REG 1 MUX TCCO THREE-STATE BUFFERS ON CELL 7 ONLY
COUT0-7
COENB
LATCHES DCM1 DCM0 RESET DIENB CIENB ADR0 ADR1 ADR2 ERASE
CLK
ADR0 ADR1 ADR2 DECODER
CELL 0 CELL 1 T REG LD
CELL 7
CELLn CLK
D
Q
AOUT0-25
FIGURE 1. FILTER CELL
7
HSP43881
0 1 6 7
26 3 ADR0.D-ADR2.D 0-18 18 SIGN EXT 18-25 RESET.D 18 (LSBs) 0-17 8
26
26
26
CELL RESULT MUX
26
+
SHADD D
26 CLR Q SHADD.D ZERO MUX 0 18 1 8-25 CLK OUTPUT BUFFER 26 RESET.D
CLK 18 MSBs SHIFTED 8 BITS TO RIGHT (BITS 0 - 17)
0 1
26 0
OUTPUT MUX RESET.D 26 CLR D Q 2
SENBL SENBH
THREE-STATE BUFFER
26 CLK SUM0-25
FIGURE 2. DF OUTPUT STAGE
The 26 least significant bits (LSBs) from either a cell accumulator or the output buffer are output on the SUM0-25 bus. The output mux determines whether the cell accumulator selected by ADR0-2 or the output buffer is output to the bus. This mux is controlled by the SHADD input signal. Control is based on the state of the SHADD during two successive clocks; in other words, the output mux selection contains memory. If SHADD is low during a clock cycle and was low during the previous clock, the output mux selects the contents of the filter cell accumulator addressed by ADR0-2. Otherwise the output mux selects the contents of the output buffer. If the ADR0-2 lines remain at the same address for more than one clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the addressed cell. Only the result available during the first clock when ADR0-2 selects the cell will be output. This does not hinder normal FIR operation since the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories where the output is required to be fixed for more than one clock.
The SUM0-25 output bus is controlled by the SENBH and SENBL signals. A low on SENBL enables bits SUM0-15. A low on SENBH enables bits SUM16-25. Thus, all 26 bits can be output simultaneously if the external system has a 26-bit or larger bus. If the external system bus is only 16 bits, the bits can be enabled in two groups of 16 and 10 bits (sign extended).
DF Arithmetic
Both data samples and coefficients can be represented as either unsigned or two's complement numbers. The TCS and TCCI inputs determine the type of arithmetic representation. Internally all values are represented by a 9-bit two's complement number. The value of the additional ninth bit depends on the arithmetic representation selected. For two's complement arithmetic, the sign is extended into the ninth bit. For unsigned arithmetic, bit-9 is 0. The multiplier output is 18 bits and the accumulator is 26 bits. The accumulator width determines the maximum possible number of terms in the sum of products without
8
HSP43881
overflow. The maximum number of terms depends also on the number system and the distribution of the coefficient and data values. Then maximum numbers of terms in the sum products are:
MAX # OF TERMS 1032 2080 2047 2064
For practical FIR filters, the coefficients are never all near maximum value, so even larger vectors are possible in practice.
Basic FIR Operation
NUMBER SYSTEM Two Unsigned Vectors Two Two's Complement:
* Two Positive Vectors * Negative Vectors * One Positive and One Negative Vector
One Unsigned and One Two's Complement Vector:
* Positive Two's Complement Vector * Negative Two's Complement Vector
1036 1028
A simple, 30MHz 8-tap filter example serves to illustrate more clearly the operation of the DF. The sequence table (Table 1) shows the results of the multiply accumulate in each cell after each clock. The coefficient sequence, Cn, enters the DF on the left and moves from left to right through the cells. The data sample sequence, Xn, enters the DF from the top, with each cell receiving the same sample simultaneously. Each cell accumulates the sum of products for one output point. Eight sums of products are calculated simultaneously, but staggered in time so that a new output is available every system clock.
TABLE 1. 30MHz, 8-TAP FIR FILTER SEQUENCE X15...X9, X8, X7...X1, X0 C0...C6, C7, C0...C6, C7
HSP43881
Y15...Y14,...Y8, Y7
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CELL 0 C7 x X0 +C6 x X1 +C5 x X2 +C4 x X3 +C3 x X4 +C2 x X5 +C1 x X6 +C0 x X7 C7 x X8 +C6 x X9 +C5 x X10 +C4 x X11 +C3 x X12 +C2 x X13 +C1 x X14 +C0 x X15
CELL 1 0 C7 x X1 +C6 x X2 +C5 x X3 +C4 x X4 C3 x X5 +C2 x X6 +C1 x X7 +C0 x X8 C7 x X9 +C6 x X10 +C5 x X11 +C4 x X12 +C3 x X13 +C2 x X14 +C1 x X15
CELL 2 0 0 C7 x X2 +C6 x X3 +C5 x X4 +C4 x X5 +C3 x X6 +C2 x X7 +C1 x X8 +C0 x X9 C7 x X10 +C6 x X11 +C5 x X12 +C4 x X13 +C3 x X14 +C2 x X15
CELL 3 0 0 0 C7 x X3 +C6 x X4 +C5 x X5 +C4 x X6 +C3 x X7 +C2 x X8 +C1 x X9 +C0 x X10 C7 x X11 +C6 x X12 +C5 x X13 +C4 x X14 +C3 x X15
CELL 4
CELL 5
CELL 6
CELL 7
SUM/CLR -
C7 x X4 +C6 x X5 +C5 x X6 +C4 x X7 +C3 x X8 +C2 x X9 +C1 x X10 +C0 x X11 C7 x X12 +C6 x X13 +C5 x X14 +C4 x X15 C7 x X5 +C6 x X6 +C5 x X7 +C4 x X8 +C3 x X9 +C2 x X10 +C1 x X11 +C0 x X12 C7 x X13 +C6 x X14 +C5 x X15 C7 x X6 +C6 x X7 +C5 x X8 +C4 x X9 +C3 x X10 +C2 x X11 +C1 x X12 +C0 x X13 +C7 x X14 +C6 x X15 C7 x X7 +C6 x X8 +C5 x X9 +C4 x X10 +C3 x X11 +C2 x X12 +C1 x X13 +C0 x X14 C7 x X15
Cell 0 (Y7) Cell 1 (Y8) Cell 2 (Y9) Cell 3 (Y10) Cell 4 (Y11) Cell 5 (Y12) Cell 6 (Y13) Cell 7 (Y14) Cell 0 (Y15)
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HSP43881
SAMPLE DATA IN (Xn) 30MHz CLOCK
3-BIT COUNTER +5V Y2 Y 1 Y 0
ADR2 ADR1 ADR0 VCC SHADD SENBH 8 DIN0-7
SENBL
26 DIENB TCS HSP43881 CLK A2 A1 A0 8 D0-D7 8 x 8 COEFF. RAM/ROM SYSTEM RESET ERASE CIN0-7 CIENB DCM1 DCM0 RESET ERASE VSS COENB TCCI COUT0-7 TCCO SUM0-25
SUM OUT (Yn)
NC
8 NC
FIGURE 3. 30MHZ, 8 TAP FIR FILTER APPLICATION SCHEMATIC
Detailed operation of the DF to perform a basic 8-tap, 8-bit coefficient, 8-bit data, 30MHz FIR filter is best understood by observing the schematic (Figure 3) and timing diagram (Figure 4). The internal pipeline length of the DF is four (4) clock cycles, corresponding to the register levels CREG (or XREG), MREG0, MREG1, and TREG (Figures 1 and 2). Therefore, the delay from presentation of data and coefficients at the DIN0-7 and CIN0-7 inputs to a sum appearing at the SUM0-25 output is: k + Td Where: k = filter length Td = 4, the internal pipeline delay of DF After the pipeline has filled, a new output sample is available every clock. The delay to last sample output from last sample input is Td. The output sums, Yn, shown in the Timing Diagram are derived from the sum of products equation: Y(n) = C(0) x X(n) + C(1) x X(n1) + C(2) x X(n -2) + C(3) x X(n -3) + C(4) x X(n -4) + C(5) x X(n -5) + C(6) x X(n -6) + C(7) x X(n -7)
Extended FIR Filter Length
Filter lengths greater that eight taps can be created by either cascading together multiple DF devices or "reusing" a single device. Using multiple devices, an FIR filter of over 1000taps can be constructed to operate at a 30MHz sample rate. Using a single device clocked at 30MHz, a FIR filter of over 1000 taps can be constructed to operate at less than a 30MHz sample rate. Combinations of these two techniques are also possible.
10
HSP43881
0 CLK RESET ERASE DIN0-7 DIENB CIN0-7 CIENB ADR0-2 SUM0-24 SHADD SENBL SENBH DCM0-1 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10 X11 X12 X13 X14 X15 X16 X17 X18
C7
C6
C5
C4
C3
C2
C1
C0
C7
C6
C5
C4
C3
C2
C1
C0
C7
C6
C5
0
1 Y7
2 Y8
3 Y9
4
5
6
7
0
Y10 Y11 Y12 Y13 Y14
YN =
K=0
7
CK x XN - K
FIGURE 4. 30MHz, 8-TAP FIR FILTER TIMING
11
SAMPLE DATA IN (Xn) C D 30MHz CLOCK Q Q
12
8 DIN0-7 DIENB TCS CLK CLK Y0 4-BIT Y1 COUNTER Y2 RESET Y3 8x16 COEFF. RAM/ROM A0 A1 A2 A3 D0-D7 TCCI 8 CIN0-7 SYSTEM RESET
+5V
+5V
ADR1 ADR0 ADR2 VCC SHADD SENBH
SENBL 25 SUM0-24 8
ADR1 ADR0 ADR2 VCC SHADD SENBH DIN0-7 DIENB
SENBL 25 SUM0-24
HSP43881 DF0 TCCO 8 COUT0-7
TCS CLK TCCI
HSP43881
HSP43881
DF1
TCCO
NC
8 CIN0-7 COUT0-7 NC
CIENB DCM1 DCM0 RESET ERASE VSS COENB
CIENB DCM1 DCM0 RESET ERASE VSS COENB
SUM OUT (Yn)
FIGURE 5. 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC
HSP43881 Cascade Configuration
To design a filter length L>8, L/8 DFs are cascaded by connecting the COUT0-7 outputs of the (i)th DF to the CIN07 inputs of the (i+1)th DF. The DIN0-7 inputs and SUM0-25 outputs of all the DFs are also tied together. A specific example of two cascaded DFs illustrates the technique (Figure 5). Timing (Figure 6) is similar to the simple 8-tap FIR, except the ERASE and SENBL/SENBH signals must be enabled independently for the two DFs in order to clear the correct accumulators and enable the SUM0-25 output signals at the proper times.
Extended Coefficient and Data Sample Word Size
The sample and coefficient word size can be extended by utilizing several DFs in parallel to get the maximum sample rate or a single DF with resulting lower sample rates. The technique is to compute partial products of 8 x 8 and combine these partial products by shifting and adding to obtain the final result. The shifting and adding can be accomplished with external adders (at full speed) or with the DF's shift and add mechanism contained in its output stage (at reduced speed).
Single DF Configuration
Using a single DF, a filter of length L>8 can be constructed by processing in L/8 passes as illustrated in the following table (Table 2) for a 16-tap FIR. Each pass is composed of Tp = 7 + L cycles and computes eight output samples. In pass i, the sample with indices i*8 to i*8 +(L1) enter the DIN0-7 inputs. The coefficients C0 -CL -1 enter the CIN0-7 inputs, followed by seven zeros. As these zeros are entered, the result samples are output and the accumulators reset. Initial filing of the pipeline is not shown in this sequence table. Filter outputs can be put through a FIFO to even out the sample rate.
Decimation/Resampling
The HSP43881 DF provides a mechanism for decimating by factors of 2, 3, or 4. From the DF filter cell block diagram (Figure 1), note the three D registers and two multiplexers in the coefficient path through the cell. These allow the coefficients to be delayed by 1, 2, or 3 clocks through the cell. The sequence table (Table 3) for a decimate by two filter illustrates the technique (internal cell pipelining ignored for simplicity). Detailed timing for a 30MHz input sample rate, 15MHz output sample rate (i.e., decimate by two), 16-tap FIR filter, including pipelining, is shown in Figure 7. This filter requires only a single HSP43881 DF.
13
0 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RESET
DF0 ERASE
14
DF1 ERASE
DIN0-7
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37
DIENB
CIN0-7
C15 C14 C13 C12 C11 C10 C9 C8
C7
C6
C5 C4
C3
C2
C1
C0 C15 C14 C13 C12 C11 C10 C9
C8
C7
C6
C5 C4
C3
C2
C1
C0 C15 C14 C13 C12 C11 C10
CIENB
HSP43881
ADR0-2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
DF0 SUM0-25
Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22
Y31 Y32 Y33
DF1 SUM0-25
Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30
SHADD
DF0 SENBL/H
DF1 SENBL/H
DCM0-1
0
YN =
K=0
15
CK x XN - K
FIGURE 6. 16-TAP 30MHz FIR FILTER TIMING USING TWO CASCADED HSP43881s
HSP43881
TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF Data Sequence X30...X9, X8, X22...X1, X0 Input Coefficient Sequence C0...C14, C15, 0...0, C0...C14, C15 Input CLK 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CELL 0 C15 x X0 +C14 x X1 +C13 x X2 +C12 x X3 +C11 x X4 +C10 x X5 +C9 x X6 +C8 x X7 +C7 x X8 +C6 x X9 +C5 x X10 +C4 x X11 +C3 x X12 +C2 x X13 +C1 x X14 +C0 x X15 0 0 0 0 0 0 0 +C0 x X16 0 0 0 0 0 0 C0 x X17 0 0 0 0 0 CELL 1 0 C15 x X1 CELL 2 0 0 C15 x X2 CELL 3 0 0 0 C15 x X3 +C14 x X4 +C13 x X5 +C12 x X6 +C11 x X7 +C10 x X8 +C9 x X9 +C8 x X10 +C7 x X11 +C6 x X12 +C5 x X13 +C4 x X14 +C3 x X15 +C2 x X16 +C1 x X17 +C0 x X18 0
0 0 0
HSP43881
...0, Y30 ...Y23, 0...0, Y22,...Y15, 0...0 CELL 5 CELL 6 CELL 7 SUM/CLR -
CELL 4
C15 x X4 C15 x X5 C15 x X6 C15 x X7 C14 x X8 C13 x X9 C12 x X10 C11 x X11 C10 x X12 C9 x X13 C8 x X14 C7 x X15 C6 x X16 C5 x X17 C4 x X18 C0 x X19 0 0 0 C0 x X20 0 0 C0 x X21 0 C3 x X19 C2 x X20 C1 x X21 C0 x X22
CELL 0 (Y15) CELL 1 (Y16) CELL 2 (Y17) CELL 3 (Y18) CELL 4 (Y19) CELL 5 (Y20) CELL 6 (Y21) CELL 7 (Y22)
15
HSP43881
TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF (Continued) Data Sequence X30...X9, X8, X22...X1, X0 Input Coefficient Sequence C0...C14, C15, 0...0, C0...C14, C15 Input CLK 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 CELL 0 C15 x X8 +C14 x X9 +C13 x X10 +C12 x X11 +C11 x X12 +C10 x X13 +C9 x X14 +C8 x X15 +C7 x X16 +C6 x X17 +C5 x X18 +C4 x X19 +C3 x X20 +C2 x X21 +C1 x X22 +C0 x X23 0 0 0 0 C0 x X24 0 0 0 C0 x X25 0 0 C0 x X27 C0 x X26 CELL 1
0
HSP43881
...0, Y30 ...Y23, 0...0, Y22,...Y15, 0...0 CELL 5 0 0 0 0 0 C15 x X13 CELL 6 0 0 0 0 0 0 C15 x X14 CELL 7 0 0 0 0 0 0 0 C15 x X15 C14 x X16 C13 x X17 C12 x X18 C11 x X19 C10 x X20 C9 x X21 C8 x X22 C7 x X23 C6 x X24 C5 x X25 C4 x X26 C3 x X27 SUM/CLR CELL 0 (Y23) CELL 1 (Y24) CELL 2 (Y25) CELL 3 (Y26) CELL 4 (Y27)
CELL 2
0
CELL 3
0 0
CELL 4 0 0 0 0 C15 x X12
C15 x X9
0 +C15 x X10
0
16
HSP43881
TABLE 3. 16-TAP DECIMATE BY TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT Data Sequence ...X2, X1, X0 Input Coefficient Sequence ...C15, C0, ...C13, C14, C15 Input CLK 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 CELL 0 C15 x X0 +C14 x X1 +C13 x X2 +C12 x X3 +C11 x X4 +C10 x X5 +C9 x X6 +C8 x X7 +C7 x X8 +C6 x X9 +C5 x X10 +C4 x X11 +C3 x X12 +C2 x X13 +C1 x X14 +C0 x X15 C15 x X16 +C14 x X17 +C13 x X18 +C12 x X19 +C11 x X20 +C10 x X21 +C9 x X22 +C8 x X23 +C7 x X24 +C6 x X25 +C5 x X26 +C4 x X27 +C3 x X28 +C2 x X29 +C1 x X30 +C0 x X31 +C14 x X31 +C14 x X31 +C14 x X31 +C14 x X31 +C14 x X31 +C14 x X31 CELL 1 0 0 C15 x X2 CELL 2 0 0 0 0 C15 x X4 CELL 3 0 0 0 0 0 0 C15 x X6
HSP43881
...Y19, -, ...Y17, -, Y15 CELL 5 0 0 0 0 0 0 0 0 0 0 C15 x X10 CELL 6 0 0 0 0 0 0 0 0 0 0 0 0 C15 x X12 CELL 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C15 x X14 +C14 x X15 +C13 x X16 +C12 x X17 +C11 x X18 +C10 x X19 +C9 x X20 +C8 x X21 +C7 x X22 +C6 x X23 +C5 x X24 +C4 x X25 +C3 x X26 +C2 x X27 +C1 x X28 +C0 x X29 C15 x X30 +C14 x X31 SUM/CLR CELL 0 (Y15) CELL 1 (Y17) CELL 2 (Y19) CELL 3 (Y21) CELL 4 (Y23) CELL 5 (Y25) CELL 6 (Y27) CELL 7 (Y29) CELL 8 (Y31)
CELL 4 0 0 0 0 0 0 0 0 C15 x X8
17
0 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RESET
ERASE
DIN0-7
X0
X1
X2
X3
X4
X5
X6
X7 X8
X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37
18
DIENB
CIN0-7
C15 C14 C13 C12 C11 C10 C9 C8 C7 C6
C5 C4 C3
C2 C1 C0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6
C5 C4 C3 C2 C1 C0 C15 C14 C13 C12 C11 C10
CIENB ADR0-2
0
1
2
3
4
5
6
7
0
1
SUM0-25
Y15
Y17
Y19
Y21
Y23
Y25
Y27
Y29
Y31
Y33
HSP43881
SHADD
SENBL
SENBH
DCM0-1
1
FIGURE 7. 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz, 15MHz OUT
HSP43881
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V Input, Output Voltage . . . . . . . . . . . . . . . . . . . GND -0.5 to VCC 0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PLCC Package . . . . . . . . . . . . . . . . . . 34 N/A PGA Package . . . . . . . . . . . . . . . . . . . 36 7 Maximum Junction Temperature PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (PLCC - Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 5% Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,763 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical One Input Voltage Logical Zero Input Voltage Logical One Output Voltage Logical Zero Output Voltage Clock Input High Clock Input Low Input Capacitance PLCC PGA Output Capacitance PLCC PGA NOTES: 2. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz. 3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 4. Output load per test load circuit and CL = 40pF. SYMBOL ICCOP ICCSB II IO VIH VIL VOH VOL VIHC VILC CIN COUT Note 3 NOTES Notes 2, 4 Note 4 TEST CONDITIONS VCC = Max CLK Frequency 20MHz VCC = Max VCC = Max, Input = 0V or VCC VCC = Max, Input = 0V or VCC VCC = Max VCC = Min IOH = 400A, VCC = Min IOL = 2mA, VCC = Min VCC = Max VCC = Min CLK Frequency 1MHz All measurements referenced to GND TA = 25oC MIN -10 -10 2.0 2.6 3.0 MAX 140 500 10 10 0.8 0.4 0.8 10 15 10 15 UNITS mA A A A V V V V V V pF pF pF pF
19
HSP43881
AC Electrical Specifications
PARAMETER TEST CONDITIONS Clock Period Clock Low Clock High Input Setup Input Hold CLK to Coefficient Output Delay Output Enable Delay Output Disable Delay CLK to SUM Output Delay Output Rise Output Fall NOTE: 5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. VCC = 5V 5%, TA = 0oC to + 70oC -20 (20MHz) SYMBOL t CP t CL t CH t IS t IH t ODC t OED t ODD t ODS t OR t OF Note 5 Note 5 Note 5 NOTES MIN 50 20 20 16 0 MAX 24 20 20 27 6 6 -25 (25.6MHz) MIN 39 16 16 14 0 MAX 20 15 15 25 6 6 -30 (30MHz) MIN 33 13 13 13 0 MAX 18 15 15 21 6 6 UNITS ns ns ns ns ns ns ns ns ns ns ns
Test Load Circuit
S1 DUT (NOTE 6) CL IOH
1.5V
IOL
EQUIVALENT CIRCUIT
NOTES: 6. Includes stray and jig capacitance. 7. Switch S1 Open for ICCSB and ICCOP Tests.
20
HSP43881 Waveforms
2.0V tCP tCH 2.0V CLK 2.0V tCL 2.0V 3.0V INPUT 0.0V CLK t IS 1.5V tIH 1.5V
4.0V 0.0V
FIGURE 8. CLOCK AC PARAMETERS
Input includes: DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RESET,DCM0-1, ADRO-2, TCS, TCCI, SHADD FIGURE 9. INPUT SETUP AND HOLD
2.0V CLK tODC, tODS SUM0-25 COUT0-7 TCCO 1.5V tOR tOF 2.0V 0.8V
SUM-25, COUTO-7, TCCO are assumed not to be in highimpedance state. FIGURE 10. SUM0-25, COUT0-7, TCCO OUTPUT DELAYS
FIGURE 11. OUTPUT RISE AND FALL TIMES
SENBL SENBH COENB
3.0V 1.5V tOED tODD 1.5V INPUT 0.0V 1.5V
DEVICE UNDER TEST
1.5V
OUTPUT
SUM0-25 COUT0-7 TCCO
HIGH IMPEDANCE
1.7V 1.3V
HIGH IMPEDANCE
NOTE: AC Testing: Inputs are driven at 3.0V for Logic and "1" and 0.0V for Logic "0". Input and output timing measurements are made at 1.5 for both a Logic "1" and "0". CLK is driven at 4.0 and 0V and measured at 2.0V. FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM
FIGURE 12. OUTPUT ENABLE, DISABLE TIMING
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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